1) Field of the Invention
The present invention relates to a semiconductor device having a decoupling capacity. More specifically, the present invention relates to a circuit to disconnect a capacitor, which functions as the decoupling capacity, from a power supply when a dielectric breakdown occurs in the capacitor.
2) Description of the Related Art
In recent years, demand for acceleration and high integration of semiconductor chips rises following improved performances of such as home electric appliances. To meet this demand, a gate area of each metal oxide semiconductor (MOS) transistor integrated in a semiconductor chip is increased. A semiconductor chip required to operate at a high rate, in particular, is intended to stabilize a power supply voltage by connecting many decoupling capacities between a power supply and a ground.
Normally, a capacitor that functions as a decoupling capacity (hereinafter, simply “capacitor”) has a MOS gate structure. In addition, the capacity uses, as a dielectric, an insulating film formed simultaneously with a gate insulating film of the MOS transistor. Therefore, if the gate insulating film of the MOS transistor is thinner following a recent advancement of a microfabrication technique, the dielectric of the capacitor is thinner accordingly. As a result, a time-dependent dielectric breakdown (TDDB) frequently occurs. Namely, a defect of a dielectric breakdown of a capacitor frequently occurs while a customer uses a semiconductor chip shipped from a manufacturer. If the TDDB occurs to the capacitor, then a short-circuit between a power supply and a ground occurs. This disadvantageously causes an increase in current consumption and a drop in the power supply voltage. It is, therefore, necessary to take measures not to cause such defects when the TDDB occurs to the capacitor after shipment.
Meanwhile, when occurrence of the TDDB to the capacitor is discovered at a semiconductor chip test conducted just before the shipment, the semiconductor chip is abandoned as a defective product even if a defective capacitor is only a part of the capacitors on the semiconductor chip. This disadvantageously deteriorates product yield. To prevent this, a semiconductor integrated circuit has been suggested in which a p channel MOS transistor (hereinafter, “PMOS”) is connected between the power supply and the capacitor, which is disconnected from the power supply when it is determined to be defective by turning off the PMOS through a signal from an external control circuit (see for example, Japanese Patent Application Laid-open No. 2003-17569 (FIGS. 1 and 2)). The product yield is improved since this semiconductor integrated circuit can be shipped as a good product by disconnecting the defective capacitor from the power supply.
According to Japanese Patent Application Laid-open No. 2003-17569, however, the capacitor that becomes defective after the shipment (in other words, while a client uses the product) cannot be disconnected from the power supply. Thus, this conventional semiconductor integrated circuit is disadvantageously incapable of dealing with the capacitor to which a defect occurs after the shipment.